Techniques for Software Filter for a/d Readings

Organisation that converts an analog signal into a digital signal

"A2D" redirects hither. For the U.South. Navy attack aircraft, see Douglas A2D Skyshark.

AD570 8-Chip Successive Approximation Analog-to-Digital Converter.

INTERSIL ICL7107. 31/ii Digit Unmarried Chip A/D Converter

In electronics, an analog-to-digital converter (ADC, A/D, or A-to-D) is a system that converts an analog bespeak, such as a audio picked up past a microphone or low-cal entering a digital camera, into a digital signal. An ADC may as well provide an isolated measurement such as an electronic device that converts an analog input voltage or current to a digital number representing the magnitude of the voltage or electric current. Typically the digital output is a ii's complement binary number that is proportional to the input, but there are other possibilities.

There are several ADC architectures. Due to the complexity and the need for precisely matched components, all but the most specialized ADCs are implemented every bit integrated circuits (ICs). These typically take the form of metal–oxide–semiconductor (MOS) mixed-signal integrated circuit chips that integrate both analog and digital circuits.

A digital-to-analog converter (DAC) performs the contrary function; it converts a digital bespeak into an analog signal.

Explanation [edit]

An ADC converts a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital betoken. The conversion involves quantization of the input, so it necessarily introduces a modest amount of error or noise. Furthermore, instead of continuously performing the conversion, an ADC does the conversion periodically, sampling the input, limiting the allowable bandwidth of the input signal.

The performance of an ADC is primarily characterized by its bandwidth and indicate-to-noise ratio (SNR). The bandwidth of an ADC is characterized primarily by its sampling charge per unit. The SNR of an ADC is influenced past many factors, including the resolution, linearity and accuracy (how well the quantization levels match the true analog signal), aliasing and jitter. The SNR of an ADC is often summarized in terms of its effective number of bits (ENOB), the number of bits of each measure it returns that are on average not noise. An ideal ADC has an ENOB equal to its resolution. ADCs are chosen to friction match the bandwidth and required SNR of the signal to be digitized. If an ADC operates at a sampling charge per unit greater than twice the bandwidth of the betoken, then per the Nyquist–Shannon sampling theorem, perfect reconstruction is possible. The presence of quantization error limits the SNR of even an platonic ADC. Nonetheless, if the SNR of the ADC exceeds that of the input bespeak, its furnishings may be neglected resulting in an essentially perfect digital representation of the analog input betoken.

Resolution [edit]

Fig. 1. An eight-level ADC coding scheme.

The resolution of the converter indicates the number of different, ie discrete, values it can produce over the allowed range of analog input values. Thus a particular resolution determines the magnitude of the quantization error and therefore determines the maximum possible signal-to-noise ratio for an platonic ADC without the utilise of oversampling. The input samples are usually stored electronically in binary course inside the ADC, and then the resolution is unremarkably expressed equally the sound chip depth. In consequence, the number of discrete values available is usually a power of ii. For example, an ADC with a resolution of viii $.25 can encode an analog input to one in 256 unlike levels (ii^viii = 256). The values tin can represent the ranges from 0 to 255 (i.east. as unsigned integers) or from −128 to 127 (i.e. equally signed integer), depending on the application.

Resolution can too exist defined electrically, and expressed in volts. The change in voltage required to guarantee a alter in the output code level is called the least significant flake (LSB) voltage. The resolution Q of the ADC is equal to the LSB voltage. The voltage resolution of an ADC is equal to its overall voltage measurement range divided past the number of intervals:

${\displaystyle Q={\dfrac {E_{\mathrm {FSR} }}{ii^{M}}},}$

where M is the ADC'due south resolution in bits and Due east _FSR is the total scale voltage range (also chosen 'span'). Due east _FSR is given by

${\displaystyle E_{\mathrm {FSR} }=V_{\mathrm {RefHi} }-V_{\mathrm {RefLow} },\,}$

where V _RefHi and 5 _RefLow are the upper and lower extremes, respectively, of the voltages that tin be coded.

Normally, the number of voltage intervals is given by

${\displaystyle Due north=2^{M},\,}$

where Thou is the ADC'south resolution in $.25.^[1]

That is, ane voltage interval is assigned in between two consecutive code levels.

Example:

• Coding scheme as in figure 1
• Full scale measurement range = 0 to 1 volt
• ADC resolution is 3 $.25: two³ = 8 quantization levels (codes)
• ADC voltage resolution, Q = one 5 / 8 = 0.125 Five.

In many cases, the useful resolution of a converter is express by the signal-to-noise ratio (SNR) and other errors in the overall system expressed as an ENOB.

Comparing of quantizing a sinusoid to 64 levels (6 $.25) and 256 levels (8 bits). The additive noise created past 6-bit quantization is 12 dB greater than the noise created past 8-chip quantization. When the spectral distribution is flat, as in this example, the 12 dB difference manifests every bit a measurable difference in the noise floors.

Quantization error [edit]

Analog to digital conversion as shown with fig. 1 and fig. two.

Quantization error is introduced by the quantization inherent in an ideal ADC. Information technology is a rounding mistake between the analog input voltage to the ADC and the output digitized value. The fault is nonlinear and betoken-dependent. In an platonic ADC, where the quantization fault is uniformly distributed between −i/2 LSB and +1/2 LSB, and the bespeak has a uniform distribution roofing all quantization levels, the Signal-to-quantization-noise ratio (SQNR) is given by

${\displaystyle \mathrm {SQNR} =20\log _{10}(2^{Q})\approx half dozen.02\cdot Q\ \mathrm {dB} \,\!}$ ^[2]

where Q is the number of quantization $.25. For case, for a 16-flake ADC, the quantization error is 96.three dB beneath the maximum level.

Quantization fault is distributed from DC to the Nyquist frequency. Consequently, if part of the ADC's bandwidth is not used, as is the example with oversampling, some of the quantization error will occur out-of-band, effectively improving the SQNR for the bandwidth in employ. In an oversampled system, racket shaping tin can be used to further increase SQNR by forcing more quantization error out of band.

Dither [edit]

In ADCs, performance tin usually exist improved using dither. This is a very small amount of random noise (e.grand. white noise), which is added to the input before conversion. Its effect is to randomize the land of the LSB based on the signal. Rather than the betoken simply getting cutting off altogether at low levels, it extends the effective range of signals that the ADC can convert, at the expense of a slight increment in noise. Annotation that dither can only increase the resolution of a sampler. It cannot ameliorate the linearity, and thus accuracy does not necessarily meliorate.

Quantization baloney in an sound signal of very depression level with respect to the flake depth of the ADC is correlated with the signal and sounds distorted and unpleasant. With dithering, the distortion is transformed into noise. The undistorted signal may be recovered accurately by averaging over fourth dimension. Dithering is also used in integrating systems such as electricity meters. Since the values are added together, the dithering produces results that are more exact than the LSB of the analog-to-digital converter.

Dither is often applied when quantizing photographic images to a fewer number of bits per pixel—the image becomes noisier but to the heart looks far more realistic than the quantized prototype, which otherwise becomes banded. This analogous procedure may help to visualize the consequence of dither on an analog audio betoken that is converted to digital.

Accurateness [edit]

An ADC has several sources of errors. Quantization mistake and (bold the ADC is intended to be linear) non-linearity are intrinsic to any analog-to-digital conversion. These errors are measured in a unit chosen the to the lowest degree significant bit (LSB). In the above example of an 8-flake ADC, an error of one LSB is 1/256 of the total signal range, or almost 0.four%.

Nonlinearity [edit]

All ADCs suffer from nonlinearity errors caused by their concrete imperfections, causing their output to deviate from a linear function (or some other role, in the instance of a deliberately nonlinear ADC) of their input. These errors can sometimes be mitigated by calibration, or prevented by testing. Of import parameters for linearity are integral nonlinearity and differential nonlinearity. These nonlinearities introduce distortion that can reduce the signal-to-racket ratio performance of the ADC and thus reduce its effective resolution.

Jitter [edit]

When digitizing a sine moving ridge ${\displaystyle ten(t)=A\sin {(ii\pi f_{0}t)}}$ , the use of a non-platonic sampling clock will result in some uncertainty in when samples are recorded. Provided that the actual sampling time incertitude due to clock jitter is ${\displaystyle \Delta t}$ , the error acquired past this phenomenon can be estimated as ${\displaystyle E_{ap}\leq |x'(t)\Delta t|\leq 2A\pi f_{0}\Delta t}$ . This will result in additional recorded racket that will reduce the effective number of bits (ENOB) below that predicted past quantization error alone. The mistake is zero for DC, small at low frequencies, merely significant with signals of high amplitude and high frequency. The effect of jitter on performance can exist compared to quantization error: ${\displaystyle \Delta t<{\frac {1}{2^{q}\pi f_{0}}}}$ , where q is the number of ADC bits.^{[ citation needed ]}

Output size (bits)	Signal Frequency
	1 Hz	1 kHz	x kHz	1 MHz	10 MHz	100 MHz	1 GHz
8	one,243 µs	i.24 µs	124 ns	i.24 ns	124 ps	12.iv ps	1.24 ps
10	311 µs	311 ns	31.1 ns	311 ps	31.ane ps	3.11 ps	0.31 ps
12	77.7 µs	77.7 ns	7.77 ns	77.7 ps	vii.77 ps	0.78 ps	0.08 ps ("77.7fs")
14	19.four µs	19.4 ns	1.94 ns	xix.iv ps	1.94 ps	0.19 ps	0.02 ps ("19.4fs")
16	4.86 µs	iv.86 ns	486 ps	4.86 ps	0.49 ps	0.05 ps ("48.five fs")	–
xviii	one.21 µs	1.21 ns	121 ps	1.21 ps	0.12 ps	–	–
twenty	304 ns	304 ps	30.4 ps	0.30 ps ("303.56 fs")	0.03 ps ("thirty.three fs")	–	–
24	18.9 ns	eighteen.9 ps	1.89 ps	0.019 ps ("18.9 fs")	-	–	–

Clock jitter is caused by phase noise.^{[3] [4]} The resolution of ADCs with a digitization bandwidth between 1 MHz and one GHz is express past jitter.^[5] For lower bandwidth conversions such as when sampling audio signals at 44.i kHz, clock jitter has a less pregnant bear upon on performance.^[6]

Sampling rate [edit]

An analog signal is continuous in time and it is necessary to convert this to a menstruation of digital values. It is therefore required to ascertain the charge per unit at which new digital values are sampled from the analog betoken. The charge per unit of new values is chosen the sampling charge per unit or sampling frequency of the converter. A continuously varying bandlimited signal can be sampled and so the original signal tin can be reproduced from the discrete-time values by a reconstruction filter. The Nyquist–Shannon sampling theorem implies that a faithful reproduction of the original indicate is only possible if the sampling rate is college than twice the highest frequency of the signal.

Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held abiding during the time that the converter performs a conversion (chosen the conversion time). An input excursion called a sample and hold performs this task—in most cases by using a capacitor to shop the analog voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input. Many ADC integrated circuits include the sample and concord subsystem internally.

Aliasing [edit]

An ADC works by sampling the value of the input at detached intervals in time. Provided that the input is sampled above the Nyquist rate, defined equally twice the highest frequency of interest, so all frequencies in the signal tin can be reconstructed. If frequencies above half the Nyquist rate are sampled, they are incorrectly detected every bit lower frequencies, a process referred to as aliasing. Aliasing occurs because instantaneously sampling a function at two or fewer times per cycle results in missed cycles, and therefore the appearance of an incorrectly lower frequency. For example, a 2 kHz sine wave being sampled at 1.5 kHz would exist reconstructed as a 500 Hz sine wave.

To avoid aliasing, the input to an ADC must be low-laissez passer filtered to remove frequencies above half the sampling rate. This filter is called an anti-aliasing filter, and is essential for a practical ADC system that is applied to analog signals with higher frequency content. In applications where protection against aliasing is essential, oversampling may be used to profoundly reduce or even eliminate information technology.

Although aliasing in most systems is unwanted, it tin be exploited to provide simultaneous down-mixing of a ring-limited high-frequency signal (meet undersampling and frequency mixer). The alias is finer the lower heterodyne of the signal frequency and sampling frequency.^[vii]

Oversampling [edit]

For economic system, signals are often sampled at the minimum charge per unit required with the result that the quantization fault introduced is white noise spread over the whole passband of the converter. If a signal is sampled at a charge per unit much higher than the Nyquist charge per unit so digitally filtered to limit it to the signal bandwidth produces the following advantages:

• Oversampling can brand it easier to realize analog anti-aliasing filters
• Improved audio bit depth
• Reduced racket, peculiarly when noise shaping is employed in addition to oversampling.

Oversampling is typically used in audio frequency ADCs where the required sampling rate (typically 44.i or 48 kHz) is very low compared to the clock speed of typical transistor circuits (>1 MHz). In this case, the performance of the ADC can exist greatly increased at little or no cost. Furthermore, as any aliased signals are also typically out of band, aliasing can oftentimes be completely eliminated using very low cost filters.

Relative speed and precision [edit]

The speed of an ADC varies by type. The Wilkinson ADC is limited by the clock rate which is processable past current digital circuits. For a successive-approximation ADC, the conversion time scales with the logarithm of the resolution, i.east. the number of bits. Wink ADCs are certainly the fastest type of the three; The conversion is basically performed in a single parallel step.

There is a potential tradeoff between speed and precision. Flash ADCs have drifts and uncertainties associated with the comparator levels results in poor linearity. To a lesser extent, poor linearity can also be an issue for successive-approximation ADCs. Here, nonlinearity arises from accumulating errors from the subtraction processes. Wilkinson ADCs have the all-time linearity of the three.^{[8] [ix]}

Sliding scale principle [edit]

The sliding scale or randomizing method can be employed to greatly improve the linearity of any type of ADC, but especially wink and successive approximation types. For whatever ADC the mapping from input voltage to digital output value is not exactly a flooring or ceiling function as information technology should be. Under normal atmospheric condition, a pulse of a particular aamplitude is ever converted to the same digital value. The problem lies in that the ranges of analog values for the digitized values are not all of the same widths, and the differential linearity decreases proportionally with the divergence from the average width. The sliding scale principle uses an averaging effect to overcome this phenomenon. A random, but known analog voltage is added to the sampled input voltage. Information technology is then converted to digital course, and the equivalent digital amount is subtracted, thus restoring it to its original value. The advantage is that the conversion has taken place at a random point. The statistical distribution of the final levels is decided by a weighted average over a region of the range of the ADC. This in turn desensitizes it to the width of whatsoever specific level.^{[10] [11]}

Types [edit]

These are several common ways of implementing an electronic ADC.

Directly-conversion [edit]

A directly-conversion or flash ADC has a depository financial institution of comparators sampling the input indicate in parallel, each firing for a specific voltage range. The comparator bank feeds a logic excursion that generates a code for each voltage range.

ADCs of this type accept a big die size and high power dissipation. They are ofttimes used for video, wideband communications, or other fast signals in optical and magnetic storage.

The circuit consists of a resistive divider network, a ready of op-amp comparators and a priority encoder. A small amount of hysteresis is built into the comparator to resolve any problems at voltage boundaries. At each node of the resistive divider, a comparing voltage is available. The purpose of the excursion is to compare the analog input voltage with each of the node voltages.

The circuit has the advantage of high speed every bit the conversion takes identify simultaneously rather than sequentially. Typical conversion time is 100 ns or less. Conversion time is limited simply by the speed of the comparator and of the priority encoder. This type of ADC has the disadvantage that the number of comparators required almost doubles for each added bit. Also, the larger the value of n, the more circuitous is the priority encoder.

Successive approximation [edit]

A successive-approximation ADC uses a comparator and a binary search to successively narrow a range that contains the input voltage. At each successive step, the converter compares the input voltage to the output of an internal digital to analog converter which initially represents the midpoint of the allowed input voltage range. At each step in this process, the approximation is stored in a successive approximation annals (SAR) and the output of the digital to analog converter is updated for a comparison over a narrower range.

Ramp-compare [edit]

A ramp-compare ADC produces a saw-molar signal that ramps upwardly or downward then quickly returns to naught. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and the timer's value is recorded. Timed ramp converters tin can be implemented economically,^[a] nevertheless, the ramp time may exist sensitive to temperature considering the circuit generating the ramp is often a simple analog integrator. A more than authentic converter uses a clocked counter driving a DAC. A special advantage of the ramp-compare organisation is that converting a second signal only requires some other comparator and another annals to store the timer value. To reduce sensitivity to input changes during conversion, a sample and agree can charge a capacitor with the instantaneous input voltage and the converter can time the fourth dimension required to discharge with a constant electric current.

Wilkinson [edit]

The Wilkinson ADC was designed by Denys Wilkinson in 1950. The Wilkinson ADC is based on the comparing of an input voltage with that produced by a charging capacitor. The capacitor is allowed to charge until a comparator determines it matches the input voltage. Then, the capacitor is discharged linearly. The time required to belch the capacitor is proportional to the amplitude of the input voltage. While the capacitor is discharging, pulses from a loftier-frequency oscillator clock are counted by a register. The number of clock pulses recorded in the register is likewise proportional to the input voltage.^{[xiii] [14]}

Integrating [edit]

An integrating ADC (also dual-gradient or multi-slope ADC) applies the unknown input voltage to the input of an integrator and allows the voltage to ramp for a stock-still time period (the run-upwards menstruation). And then a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero (the run-downwards menstruum). The input voltage is computed equally a function of the reference voltage, the abiding run-up time menstruation, and the measured run-down time period. The run-down time measurement is ordinarily fabricated in units of the converter's clock, so longer integration times allow for higher resolutions. Likewise, the speed of the converter tin be improved by sacrificing resolution. Converters of this type (or variations on the concept) are used in most digital voltmeters for their linearity and flexibility.

Accuse balancing ADC

The principle of charge balancing ADC is to first catechumen the input signal to a frequency using a voltage-to-frequency converter. This frequency is then measured by a counter and converted to an output code proportional to the analog input. The main advantage of these converters is that it is possible to transmit frequency even in a noisy environment or in isolated form. However, the limitation of this circuit is that the output of the voltage-to-frequency converter depends upon an RC product whose value cannot be accurately maintained over temperature and time.

Dual-slope ADC

The analog part of the circuit consists of a high input impedance buffer, precision integrator and a voltage comparator. The converter kickoff integrates the analog input signal for a fixed duration and so it integrates an internal reference voltage of reverse polarity until the integrator output is zero. The principal disadvantage of this excursion is the long duration time. They are particularly suitable for accurate measurement of slowly varying signals such as thermocouples and weighing scales.

Delta-encoded [edit]

A delta-encoded or counter-ramp ADC has an upwardly-downwardly counter that feeds a digital to analog converter (DAC). The input signal and the DAC both get to a comparator. The comparator controls the counter. The circuit uses negative feedback from the comparator to adjust the counter until the DAC'southward output matches the input signal and number is read from the counter. Delta converters have very wide ranges and high resolution, merely the conversion time is dependent on the input signal behavior, though it will always have a guaranteed worst-example. Delta converters are often very skilful choices to read real-world signals as most signals from concrete systems practise not modify abruptly. Some converters combine the delta and successive approximation approaches; this works peculiarly well when loftier frequency components of the input betoken are known to exist small-scale in magnitude.

Pipelined [edit]

A pipelined ADC (also called subranging quantizer) uses two or more conversion steps. Showtime, a coarse conversion is washed. In a second step, the difference to the input signal is determined with a digital to analog converter (DAC). This deviation is then converted more than precisely, and the results are combined in the last footstep. This can exist considered a refinement of the successive-approximation ADC wherein the feedback reference betoken consists of the interim conversion of a whole range of bits (for example, four bits) rather than just the side by side-most-significant bit. By combining the merits of the successive approximation and flash ADCs this type is fast, has a high resolution, and can exist implemented efficiently.

Sigma-delta [edit]

A sigma-delta ADC (also known as a delta-sigma ADC) oversamples the incoming signal by a large gene using a smaller number of $.25 than required are converted using a wink ADC and filters the desired signal band. The resulting indicate, along with the error generated by the discrete levels of the flash, is fed back and subtracted from the input to the filter. This negative feedback has the event of noise shaping the quantization mistake that information technology does not appear in the desired signal frequencies. A digital filter (decimation filter) follows the ADC which reduces the sampling rate, filters off unwanted noise signal and increases the resolution of the output.

Time-interleaved [edit]

A fourth dimension-interleaved ADC uses 1000 parallel ADCs where each ADC samples data every Thou:thursday cycle of the effective sample clock. The result is that the sample rate is increased Yard times compared to what each individual ADC tin can manage. In practice, the individual differences between the M ADCs degrade the overall performance reducing the spurious-gratuitous dynamic range (SFDR).^[xv] Still, techniques exist to correct for these time-interleaving mismatch errors.^[16]

Intermediate FM stage [edit]

An ADC with an intermediate FM phase outset uses a voltage-to-frequency converter to produce an aquiver bespeak with a frequency proportional to the voltage of the input betoken, and so uses a frequency counter to convert that frequency into a digital count proportional to the desired signal voltage. Longer integration times allow for college resolutions. Likewise, the speed of the converter can be improved past sacrificing resolution. The two parts of the ADC may be widely separated, with the frequency betoken passed through an opto-isolator or transmitted wirelessly. Some such ADCs utilize sine moving ridge or square wave frequency modulation; others apply pulse-frequency modulation. Such ADCs were once the about popular way to show a digital display of the condition of a remote analog sensor.^{[17] [18] [19] [20] [21]}

Fourth dimension-stretch [edit]

A Fourth dimension-stretch analog-to-digital converter (TS-ADC) digitizes a very wide bandwidth analog signal, that cannot exist digitized by a conventional electronic ADC, by time-stretching the signal prior to digitization. It normally uses a photonic preprocessor to time-stretch the signal, which effectively slows the bespeak down in fourth dimension and compresses its bandwidth. As a outcome, an electronic ADC, that would have been also slow to capture the original point, can at present capture this slowed-down signal. For continuous capture of the betoken, the frontend also divides the signal into multiple segments in addition to time-stretching. Each segment is individually digitized by a split electronic ADC. Finally, a digital betoken processor rearranges the samples and removes whatsoever distortions added by the preprocessor to yield the binary data that is the digital representation of the original analog signal.

Commercial [edit]

In many cases, the near expensive role of an integrated circuit is the pins, because they make the package larger, and each pivot has to be connected to the integrated circuit'due south silicon. To salvage pins, information technology is common for ADCs to send their data one flake at a time over a series interface to the computer, with each bit coming out when a clock betoken changes state. This saves quite a few pins on the ADC package, and in many cases, does not make the overall pattern any more than complex.

Commercial ADCs often take several inputs that feed the aforementioned converter, commonly through an analog multiplexer. Unlike models of ADC may include sample and hold circuits, instrumentation amplifiers or differential inputs, where the quantity measured is the difference between two inputs.

Applications [edit]

Music recording [edit]

Analog-to-digital converters are integral to 2000s era music reproduction technology and digital audio workstation-based sound recording. People often produce music on computers using an analog recording and therefore demand analog-to-digital converters to create the pulse-lawmaking modulation (PCM) data streams that get onto compact discs and digital music files. The electric current crop of analog-to-digital converters utilized in music tin sample at rates up to 192 kilohertz. Considerable literature exists on these matters, simply commercial considerations often play a significant role. Many recording studios record in 24-flake/96 kHz (or higher) pulse-lawmaking modulation (PCM) or Straight Stream Digital (DSD) formats, and then downsample or decimate the signal for Meaty Disc Digital Audio production (44.1 kHz) or to 48 kHz for commonly used radio and tv set broadcast applications because of the Nyquist frequency and hearing range of humans.

Digital signal processing [edit]

ADCs are required to procedure, shop, or ship virtually any analog signal in digital class. TV tuner cards, for example, use fast video analog-to-digital converters. Wearisome on-chip 8, 10, 12, or 16 bit analog-to-digital converters are common in microcontrollers. Digital storage oscilloscopes need very fast analog-to-digital converters, also crucial for software defined radio and their new applications.

Scientific instruments [edit]

Digital imaging systems commonly use analog-to-digital converters in digitizing pixels. Some radar systems commonly use analog-to-digital converters to convert signal force to digital values for subsequent signal processing. Many other in situ and remote sensing systems unremarkably use analogous technology. The number of binary bits in the resulting digitized numeric values reflects the resolution, the number of unique discrete levels of quantization (signal processing). The correspondence between the analog signal and the digital signal depends on the quantization error. The quantization process must occur at an adequate speed, a constraint that may limit the resolution of the digital signal. Many sensors in scientific instruments produce an analog signal; temperature, pressure level, pH, light intensity etc. All these signals can be amplified and fed to an ADC to produce a digital number proportional to the input signal.

Rotary encoder [edit]

Some non-electronic or only partially electronic devices, such as rotary encoders, can also be considered ADCs. Typically the digital output of an ADC volition be a two's complement binary number that is proportional to the input. An encoder might output a Gray lawmaking.

Displaying [edit]

Flat panel displays are inherently digital and need an ADC to process an analog signal such as blended or VGA.

Electric symbol [edit]

Testing [edit]

Testing an Analog to Digital Converter requires an analog input source and hardware to send control signals and capture digital data output. Some ADCs besides require an authentic source of reference signal.

The primal parameters to test an ADC are:

1. DC offset fault
2. DC proceeds mistake
3. Signal to racket ratio (SNR)
4. Full harmonic distortion (THD)
5. Integral nonlinearity (INL)
6. Differential nonlinearity (DNL)
7. Spurious free dynamic range
8. Power dissipation

See as well [edit]

• Adaptive predictive coding, a blazon of ADC in which the value of the signal is predicted past a linear function
• Audio codec
• Beta encoder
• Digitization
• Digital betoken processing
• Integral linearity
• Modem

Notes [edit]

1. ^ A very elementary (nonlinear) ramp converter tin be implemented with a microcontroller and ane resistor and capacitor.^[12]

References [edit]

1. ^ "Principles of Data Acquisition and Conversion" (PDF). Texas Instruments. April 2015. Retrieved October eighteen, 2016.
2. ^ Lathi, B.P. (1998). Modern Digital and Analog Advice Systems (tertiary ed.). Oxford Academy Press.
3. ^ "Maxim App 800: Pattern a Low-Jitter Clock for High-Speed Data Converters", maxim-ic.com, July 17, 2002
4. ^ "Jitter effects on Analog to Digital and Digital to Analog Converters" (PDF) . Retrieved August nineteen, 2012.
5. ^ Löhning, Michael; Fettweis, Gerhard (2007). "The effects of aperture jitter and clock jitter in wideband ADCs". Computer Standards & Interfaces Archive. 29 (1): 11–eighteen. CiteSeerXten.1.i.iii.9217. doi:10.1016/j.csi.2005.12.005.
6. ^ Redmayne, Derek; Steer, Alison (December 8, 2008), "Understanding the effect of clock jitter on high-speed ADCs", eetimes.com
7. ^ "RF-Sampling and GSPS ADCs – Breakthrough ADCs Revolutionize Radio Architectures" (PDF). Texas Instruments. Retrieved November 4, 2013.
8. ^ Knoll (1989, pp. 664–665)
9. ^ Nicholson (1974, pp. 313–315)
10. ^ Knoll (1989, pp. 665–666)
11. ^ Nicholson (1974, pp. 315–316)
12. ^ "Atmel Application Notation AVR400: Low Cost A/D Converter" (PDF). atmel.com.
13. ^ Knoll (1989, pp. 663–664)
14. ^ Nicholson (1974, pp. 309–310)
15. ^ Vogel, Christian (2005). "The Affect of Combined Aqueduct Mismatch Effects in Time-interleaved ADCs". IEEE Transactions on Instrumentation and Measurement. 55 (1): 415–427. CiteSeerX10.1.1.212.7539. doi:x.1109/TIM.2004.834046. S2CID 15038020.
16. ^ Gabriele Manganaro; David H. Robertson (July 2015), Interleaving ADCs: Unraveling the Mysteries, Analog Devices, retrieved Oct 7, 2021
17. ^ Analog Devices MT-028 Tutorial: "Voltage-to-Frequency Converters" by Walt Kester and James Bryant 2009, evidently adapted from Kester, Walter Allan (2005) Data conversion handbook, Newnes, p. 274, ISBN 0750678410.
18. ^ Microchip AN795 "Voltage to Frequency / Frequency to Voltage Converter" p. 4: "13-bit A/D converter"
19. ^ Carr, Joseph J. (1996) Elements of electronic instrumentation and measurement, Prentice Hall, p. 402, ISBN 0133416860.
20. ^ "Voltage-to-Frequency Analog-to-Digital Converters". globalspec.com
21. ^ Pease, Robert A. (1991) Troubleshooting Analog Circuits, Newnes, p. 130, ISBN 0750694998.

• Knoll, Glenn F. (1989). Radiation Detection and Measurement (2nd ed.). New York: John Wiley & Sons. ISBN978-0471815044.
• Nicholson, P. W. (1974). Nuclear Electronics. New York: John Wiley & Sons. pp. 315–316. ISBN978-0471636977.

Farther reading [edit]

• Allen, Phillip E.; Holberg, Douglas R. (2002). CMOS Analog Circuit Design. ISBN978-0-xix-511644-one.
• Fraden, Jacob (2010). Handbook of Modernistic Sensors: Physics, Designs, and Applications. Springer. ISBN978-1441964656.
• Kester, Walt, ed. (2005). The Data Conversion Handbook. Elsevier: Newnes. ISBN978-0-7506-7841-four.
• Johns, David; Martin, Ken (1997). Analog Integrated Circuit Design. ISBN978-0-471-14448-9.
• Liu, Mingliang (2006). Demystifying Switched-Capacitor Circuits. ISBN978-0-7506-7907-vii.
• Norsworthy, Steven R.; Schreier, Richard; Temes, Gabor C. (1997). Delta-Sigma Data Converters. IEEE Press. ISBN978-0-7803-1045-2.
• Razavi, Behzad (1995). Principles of Data Conversion System Blueprint. New York, NY: IEEE Printing. ISBN978-0-7803-1093-iii.
• Ndjountche, Tertulien (May 24, 2011). CMOS Analog Integrated Circuits: High-Speed and Ability-Efficient Design. Boca Raton, FL: CRC Press. ISBN978-1-4398-5491-4.
• Staller, Len (February 24, 2005). "Understanding analog to digital converter specifications". Embedded Systems Design.
• Walden, R. H. (1999). "Analog-to-digital converter survey and analysis". IEEE Journal on Selected Areas in Communications. 17 (four): 539–550. CiteSeerX10.ane.i.352.1881. doi:10.1109/49.761034.

External links [edit]

• An Introduction to Delta Sigma Converters A very nice overview of Delta-Sigma converter theory.
• Digital Dynamic Analysis of A/D Conversion Systems through Evaluation Software based on FFT/DFT Assay RF Expo East, 1987
• Which ADC Architecture Is Correct for Your Awarding? article past Walt Kester
• ADC and DAC Glossary Archived Nov 24, 2009, at the Wayback Machine Defines commonly used technical terms.
• Introduction to ADC in AVR – Analog to digital conversion with Atmel microcontrollers
• Bespeak processing and system aspects of fourth dimension-interleaved ADCs.
• Explanation of analog-digital converters with interactive principles of operations.
• MATLAB Simulink model of a simple ramp ADC.

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Source: https://en.wikipedia.org/wiki/Analog-to-digital_converter

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